library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg23 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
selector : in std_LOGIC;
D : in std_logic_vector (11 downto 0);
resultado: out std_logic_vector (11 downto 0);
Q : in std_logic_vector (11 downto 0));

end reg23;
architecture Behavioral of reg23 is
constant s0 : std_logic_vector(11 downto 0) := B"000000000000";
begin
process (clk,reset,selector)
begin
if reset='1' then resultado <=s0;
elsif rising_edge (clk) then
			if(selector='1')
				then resultado <= D;
			elsif (selector='0')
				then resultado <= Q;
			else resultado <= s0;	
			end if;
		end if;
end process;
end Behavioral;